Mohamed Tarek
@mohamedtareq24CSE MSc student at Ain shams University Cairo, with hands on experience in ASICs & FPGA design flows.
Language Breakdown
Lines of code distribution across 18 owned repositories
I-Shaped Developer
I-shapedSpecialist — deep expertise in Verilog
Collaboration Network
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Repos
20
PRs
0
Growth
+18%
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Coding Streak
Contribution activity over the past year
openmanus
@openmanus-ai
Yaseen Salah
@yaseensalah
Hossam Hassan
@hossamfadeel
Kareem Mamdouh
@KareemMamdouhHassan
Ahmed Ramadan
@ahmed-ramadan16
Top Repositories
RTL to GDSII flow of a low Power configurable multi clock digital system
My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools
FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA
Custom AXI FIR IP Tested on Avnet U96 Zynq MPSoC kit
This is a documentation for the final project of IEEE CUSB 23 Digital Electonics Workshop, the project was FPGA implemented
An Elastic Buffer Design and a UVM Verification environment for verifying USB 3 Gen 1 EB
A Demo showcasing the integration of custom HW IP + Xilinx IPs & a petalinux generated distro
PyUVM decoupled from cocotb, patched with asyncio to be used for Hardware-In-Loop HIL testing
My AUC Silicon Sprint Project a tiny 1D-CNN accelerator generated via the HLS4ML Library, taped out in Sky Water 130nm using LibreLane
Open Source Impact
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